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vishay siliconix sic417 document number: 69062 s10-1367-rev. d, 14-jun-10 www.vishay.com 1 microbuck tm sic417 10-a, 28-v integrated buck re gulator with programmable ldo description the vishay siliconix sic417 is an advanced stand-alone synchronous buck regulator featuring integrated power mosfets, bootstrap diode, and a programmable ldo in a space-saving mlpq 5 x 5 - 32 pin package. the sic417 is capable of operating with all ceramic solutions and switching frequencies up to 1 mhz. the programmable frequency, synchronous operation and selectable power-save allow operation at high efficiency across the full range of load current. the internal programmable ldo may be used to supply 5 v for the gate drive circuits or it may be bypassed with an external 5 v for optimum efficiency and used to drive external n-channel mosfets or other loads. additional features include cycle-by-cycle current limit, voltage soft-start, under-voltage protection, programmable over-current protection, so ft shutdown and selectable power-save. the vishay siliconix sic417 also provides an enable input and a power good output. features ? high efficiency > 92 % ? internal power mosfets: high-side r ds(on) = 27 m low-side r ds(on) = 9 m ? integrated bootstrap diode ? integrated configurable 150 ma ldo with bypass logic ? temperature compensated current limit ? pseudo fixed-frequency adaptive on-time control ? all ceramic solution enabled ? programmable input uvlo threshold ? independent enable pin for switcher and ldo ? selectable ultra-sonic power-save mode ? internal soft-sta rt and soft-shutdown ? 1 % internal reference voltage ? power good output a nd over voltage protection ? halogen-free according to iec 61249-2-21 definition ? compliant to rohs directive 2002/95/ec applications ? notebook, desktop and server computers ? digital hdtv and digital consumer applications ? networking and telecommunication equipment ? printers, dsl and stb applications ? embedded applications ? point of load power supplies typical application circuit product summary input voltage range 3 v to 28 v output voltage range 0.5 v to 5.5 v operating frequency 200 khz to 1 mhz continuous output current 10 a peak efficiency 95 % at 300 khz package mlpq 5 mm x 5 mm 15 6 13 8 p good e n -p sa v e e n -ldo 32 26 29 3 2 7 31 30 5 1 14 12 27 pwm controller dh v 5 v v i n bst v ldo fbl lx e n /ps v i lim p good e n l p g n d t o n v out a g n d fb dl
www.vishay.com 2 document number: 69062 s10-1367-rev. d, 14-jun-10 vishay siliconix sic417 pin configuration fb fbl v 5 v a g n d v out v i n v ldo bst lx lx p g n d p g n d p g n d p g n d p g n d p g n d v i n v i n v i n dh lx dl p g n d p g n d e n l t o n a g n d e n /ps v lx i lim p good lx pa d 1 a g n d 34 pa d 2 v i n 35 pa d 3 lx 33 pin description pin number symbol description 1fb feedback input for switching regulator. connect to an external resistor divider from output to program the output voltage. 2 fbl feedback input for the ldo. connect to an external resistor divider from v ldo to program the v ldo output. 3v5v 5 v power input for internal analog circuits and gate dr ives. connect to external 5 v supply or configure the ldo for 5 v and connect to v ldo . 4, 30, pad 1 a gnd analog ground. 5v out output voltage input to the sic417. additionally , may be used to bypass ldo to supply v ldo directly. 6, 9 - 11, pad 2 v in input supply voltage. 7v ldo ldo output. 8bst bootstrap pin. a capacitor is connected between bst to lx to develop the floating voltage for the high-side gate drive. 12 dh high-side gate drive - do not connect this pin. 14 dl low-side gate drive - do not connect this pin. 13, 23 - 25, 28, pa d 3 lx switching (phase) node. 15-22 p gnd power ground. 26 p good open-drain power good indicator. high impedance indicates power is good. an external pull-up resistor is required. 27 i lim current limit sense point - to program th e current limit connect a resistor from i lim to lx. 29 en/psv tri-state pin. enable input for switching regulator. connect en to a gnd to disable the switching regulator. float pin for forced continuous and pull high for power-save mode. 31 t on on-time set input. set the on-time by a seri es resistor to the input supply voltage. 32 enl enable input for the ldo. connect enl to a gnd to disable the ldo. ordering information part number package SIC417CD-T1-E3 mlpq55-32 sic417db evaluation board
document number: 69062 s10-1367-rev. d, 14-jun-10 www.vishay.com 3 vishay siliconix sic417 functional block diagram stresses beyond those listed under "absolute maximum ratings" may c ause permanent damage to the device. these are stress rating s only, and functional operation of the device at thes e or any other conditions beyond those indi cated in the operational sections of t he specifications is not implied. exposure to absolute ma ximum rating/conditions for extended peri ods may affect device reliability. note: for proper operation, the device should be used within the recommended conditions. v i n v i n 6, 9 - 11 pad 3 bst lx 13, 23 - 25 2 8 , pad 3 p g n d 15-22 i lim 27 v 5 v dl v 5 v e n l 32 v i n ldo mux y a b fbl v ldo v out t o n fb 2 7 5 1 31 soft start a g n d 3 26 29 control and stat u s v alley 1 - limit zero cross detector gate dri v e control reference 1.20.21 pa d 1 + - fb comparator bypass comparator v 5 v v 5 v pgd e n /ps v 8 absolute maximum ratings t a = 25 c, unless otherwise noted parameter symbol min. max. unit lx to p gnd voltage v lx - 0.3 + 30 v lx to p gnd voltage (transient - 100 ns) v lx - 2 + 30 v in to p gnd voltage v in - 0.3 + 30 v en maximum voltage v en - 0.3 v in bst bootstrap to lx; v5v to p gnd - 0.3 + 6.0 a gnd to p gnd v ag-pg - 0.3 + 0.3 en/psv, p good , i lim , v out , v ldo , fb, fbl to gnd - 0.3 + (v5v + 0.3) t on to p gnd - 0.3 + (v5v - 1.5) bst to p gnd - 0.3 + 35 recommended operating conditions parameter symbol min. typ. max. unit input voltage v in 3.0 28 v v5v to p gnd v5v 4.5 5.5 v out to p gnd v out 0.5 5.5 thermal resistance ratings parameter symbol min. typ. max. unit storage temperature t stg - 40 + 150 c maximum junction temperature t j - 150 operation junction temperature t j - 25 + 125
www.vishay.com 4 document number: 69062 s10-1367-rev. d, 14-jun-10 vishay siliconix sic417 notes: a. this device is esd sensitive. use of standard esd handling precautions is required. b. calculated from package in still air, mounted to 3 x 4.5 (i n), 4 layer fr4 pcb with therma l vias under the exposed pad per j esd51 standards. exceeding the above specific ations may result in permanent damage to the devic e or device malfunction. operation outside of the parameters specififed in the electrical characte risticsw section is not recommended. thermal resistance, junction-to-ambient b high-side mosfet low-side mosfet p w m controller and ldo thermal resistance 25 20 50 c/ w peak ir reflow temperature t reflow - 260 c thermal resistance ratings electrical specifications parameter symbol test conditions unless specified v in = 12 v, v5v = 5 v, t a = + 25 c for typ., - 25 c to + 85 c for min. and max., t j = < 125 c min. typ. max. unit input supplies v in input voltage v in 328 v v5v voltage v5v 4.5 5.5 v in uvlo threshold voltage a v in_uv+ sensed at enl pin, rising edge 2.4 2.6 2.95 v in_uv- sensed at enl pin, falling edge 2.235 2.4 2.565 v in uvlo hysteresis v in_uv_hy en/psv = high 0.2 v5v uvlo threshold voltage v 5v_uv+ measured at v5v pin, rising edge 3.7 3.9 4.1 v 5v_uv- measured at v5v pin, falling edge 3.5 3.6 3.75 v5v uvlo hysteresis v 5v_uv_hy 0.3 v in supply current i in en/psv, enl = 0 v, v in = 28 v 8.5 20 a standby mode: enl = v5v, en/psv = 0 v 130 v5v supply current i 5v en/psv, enl = 0 v 3 7 en/psv = v5v, no load (f s w = 25 khz), v fb > 500 mv b 2 ma f s w = 250 khz, en/psv = floating, no load b 10 controller f b on-time threshold v fb-th static v in and load, - 40 c to + 85 c 0.495 0.5 0.505 v frequency range f p w m continuous mode 200 1000 khz bootstrap switch resistance 10 timing on-time t on continuous mode operation v in = 15 v, v out = 5 v, f s w = 300 khz, r ton = 133 k 999 1110 1220 ns minimum on-time b t on 50 minimum off-time b t off 250 soft start soft start time b t ss i out = i lim /2 0.85 ms analog inputs/outputs v out input resistance r o-in 500 k current sense zero-crossing detector threshold voltage v sense-th lx-p gnd - 3 0 + 3 mv power good power good threshold voltage pg_v th internal reference 500 mv - 10 % + 20 % v start-up delay time pg_t d v en = 0 v 2 ms fault (noise-immunity) delay time b pg_i cc v en = 0 v 5 s power good leakage current pg_i lk v en = 0 v 1 a power good on-resistance pg_r ds-on v en = 0 v 10
document number: 69062 s10-1367-rev. d, 14-jun-10 www.vishay.com 5 vishay siliconix sic417 notes: a. v in uvlo is programmable using a resistor divider from v in to enl to a gnd . the enl voltage is compared to an internal reference. b. guaranteed by design. c. the switch-over threshold is the maximum voltage diff erential between the v ldo and v out pins which ensures that v ldo will internally switch-over to v out . the non-switch-over threshold is the minimum voltage diff erential between the v ldo and v out pins which ensures that v ldo will not switch-over to v out . d. the ldo drop out voltage is the voltage at which the ldo output drops 2 % below th e nominal regulation point. electrical characteristics fault protection i lim source current i lim 10 a valley current limit r ilim = 5.9 k 6810a i lim comparator offset voltage v ilm-lk w ith respect to a gnd - 10 0 + 10 mv output under-voltage fault v ouv_fault v fb with respect to internal 500 mv reference, 8 consecutive clocks - 25 % smart power-save protection threshold voltage b p save_vth v fb with respect to internal 500 mv reference + 10 % over-voltage protection threshold v fb with respect to internal 500 mv reference + 20 over-voltage fault delay b t ov-delay 5s over temperature shutdown b t shut 10 c hysteresis 150 c logic inputs/outputs logic input high voltage v in+ en, enl, psv 2 v logic input low voltage v in- 0.4 en/psv input bias current i en- en/psv = v5v or a gnd - 10 + 10 a enl input bias current v in = 28 v 11 18 fbl, fb input bias current fbl_i lk fbl, fb = v5v or a gnd - 1 + 1 linear dropout regulator fbl accuracy fbl acc v ldo load = 10 ma 0.735 0.75 0.765 v ldo current limit ldo_i lim start-up and foldback, v in = 12 v 85 ma operating current limit, v in = 12 v 135 200 v ldo to v out switch-over threshold c v ldo-bps - 140 + 140 mv v ldo to v out non-switch-over threshold c v ldo-nbps - 450 + 450 v ldo to v out switch-over resistance r ldo v out = 5 v 2 ldo drop out voltage d from v in to v vldo , v vldo = + 5 v, i vldo = 100 ma 1.2 v electrical specifications parameter symbol test conditions unless specified v in = 12 v, v5v = 5 v, t a = + 25 c for typ., - 25 c to + 85 c for min. and max., t j = < 125 c min. typ. max. unit efficiency vs. output current (v out = 1.2 v) i out (a) efficiency ( % ) 50 55 60 65 70 75 8 0 8 5 90 95 100 0 1234 56 7 8 910 v i n =9 v v i n = 19 v
www.vishay.com 6 document number: 69062 s10-1367-rev. d, 14-jun-10 vishay siliconix sic417 electrical characteristics frequency vs. i out , (v out = 1.2 v) start up time: v in = 12 v, v out = 1.2 v, i out = 0 a transient response: v in = 12 v, v out = 1.2 v, i out = 10 a to 5 a, di/dt = 0.5 a/s i out (a) fre qu ency (khz) 0 50 100 150 200 250 300 0 1234 56 7 8 910 v i n =9 v v i n = 19 v load regulation, (v out = 1.2 v) p good delay after start up time: v in = 12 v, v out = 1.2 v, i out = 0 a transient response: v in = 12 v, v out = 1.2 v, i out = 5 a to 10 a, di/dt = 0.5 a/s i out (a) v out ( v ) 1.15 1.2 1.25 1.3 1.35 0 1234 56 7 8 910 v i n =9 v v i n = 19 v
vishay siliconix sic417 document number: 69062 s10-1367-rev. d, 14-jun-10 www.vishay.com 7 electrical characteristics applications information sic417 synchronous buck converter the sic417 is a step down synchronous buck dc-to-dc converter with integrated power fets and programmable ldo. the sic417 is capable of 10 a operation at very high efficiency in a tiny 5 mm x 5 mm - 32 pin package. the programmable operating frequency range of 200 khz to 1 mhz, enables the user to optimize the solution for minimum board space and optimum efficiency. the buck controller employs pseudo-fixed frequency adaptive on-time control. this control scheme allows fast transient response thereby lowering the size of the power components used in the system. input voltage range the sic417 requires two input supplies for normal operation: v in and v5v. v in operates over the wide range from 3 v to 28 v. v5v requires a 5 v supply input that can be an external source or the internal ldo configured to supply 5 v. w hen v in is less than ~ 6 v then an external 5 v supply must be tied to v5v. pseudo-fixed frequency ad aptive on-time control the p w m control method used for the sic417 is pseudo-fixed frequency, adaptive on-time, as shown in figure 1. the ripple voltage gener ated at the output capacitor esr is used as a p w m ramp signal. this ripple is used to trigger the on-time of the controller. the adaptive on-time is determ ined by an internal oneshot timer. w hen the one-shot is triggered by the output ripple, the device sends a single on-time pulse to the highside mosfet. the pulse period is determined by v out and v in ; the period is proportional to output voltage and inversely proportional to input voltage. w ith this adaptive on-time arrangement, the device automatically anticipates the on-time needed to regulate v out for the present v in condition and at the selected frequency. the adaptive on-time control ha s significant advantages over traditional control methods used in the controllers today. ? reduced component count by eliminating dcr sense or current sense resistor as no need of a sensing inductor current. ? reduced saves external components used for compensation by eliminating the no error amplifier and other components. ? ultra fast transient response because of fast loop, absence of error amplifier speeds up the transient response. ? predictable frequency spread because of constant on-time architecture. ? fast transient response enables operation with minimum output capacitance overall, superior performance compared to fixed frequency architectures. over current protection: v in = 12 v, v out = 1.2 v ultra-sonic power-save at i out = 0 a figure 1 - output ripple and pwm control method v i n c i n v lx q1 q2 l esr + fb v lx t o n v fb c out v out fb threshold
www.vishay.com 8 document number: 69062 s10-1367-rev. d, 14-jun-10 vishay siliconix sic417 on-time one-shot generator (t on ) and operating frequency the sic417 have an internal on-time one-shot generator which is a comparator t hat has two inputs. the fb comparator output goes high when vfb is less than the internal 500 mv reference. this feeds into the gate drive and turns on the high-side mosfet, and also starts the one-shot timer. the one-shot timer uses an internal comparator and a capacitor. one comparator input is connected to v out , the other input is connected to the capacitor. w hen the on-time begins, the internal capacitor charges from zero volts through a current which is proportional to v in . w hen the capacitor voltage reaches v out , the on-time is completed and the high-side mosfet turn s off. the figure 2 shows the on-chip implementation of on-time generation. this method automatically pr oduces an on-time that is proportional to v out and inversely proportional to v in . under steady-state conditions, th e switching frequency can be determined from the on-time by the following equation. the sic417 uses an external re sistor to set the ontime which indirectly sets the frequency. the on-time can be programmed to provide operating frequency from 200 khz to 1 mhz using a resistor between the t on pin and ground. the resistor value is selected by the following equation. the maximum r ton value allowed is shown by the following equation. v out voltage selection the switcher output voltage is regulated by comparing v out as seen through a resistor divider at the fb pin to the internal 500 mv reference voltage, see figure 3. as the control method regulates the valley of the output ripple voltage, the dc output voltage v out is off set by the output ripple according to the following equation. v out = 0.5 x (1 + r 1 /r 2 ) + v ripple /2 enable and power-save inputs the en/psv and enl inputs are used to enable or disable the switching regulator and the ldo. w hen en/psv is low (grounded), the switching regulator is off and in its lowest power state. w hen off, the output of the switching regulator soft-discharges the output into a 15 internal resistor via the v out pin. w hen en/psv is allowed to float, the pin voltage will fl oat to 1.5 v. the switching regulator turns on with power-save disabled and all switching is in forced continuous mode. w hen en/psv is high (above 2. 0 v), the switching regulator turns on with ultra-sonic power-save enabled. the sic417 ultra-sonic power-save operation maintains a minimum switching frequency of 25 khz, for applications with stringent audio requirements. the enl input is used to control the internal ldo. this input serves a second function by acting as a v in uvlo sensor for the switching regulator. the ldo is off when enl is low (grounded). w hen enl is a logic high but below the v in uvlo threshold (2.6 v typical), then the ldo is on and the switcher is off. w hen enl is above the v in uvlo threshold, the ldo is enabled and the switcher is also enabled if the en/psv pin is not grounded. forced continuous mode operation the sic417 operates the switcher in forced continuous mode (fcm) by floating the en/psv pin (see figure 4). in this mode one of the power mosf ets is always on, with no intentional dead time other than to avoid cross-conduction. this feature results in uniform frequency across the full load range with the trade-off being poor efficiency at light loads due to the high-frequency switching of the mosfets. figure 2 - on-time generation fb 500 m v - + v out v i n r ton on-time = k x r ton x ( v out/ v i n ) fb comparator one-shot timer gate dri v es dh dl q1 q2 l q1 esr fb v out c out v lx + f sw = v out t o n x v i n r ton = (t o n - 10 ns) x v i n 25 pf x v out r ton_max = v i n _mi n 15 a figure 3 - output voltage selection v out r 1 r 2 to fb pin
vishay siliconix sic417 document number: 69062 s10-1367-rev. d, 14-jun-10 www.vishay.com 9 ultrasonic powe r-save operation the sic417 provides ultra-sonic power-save operation at light loads, with the minimum operating frequency fixed at 25 khz. this is accomplished using an internal timer that monitors the time between consecutive high-side gate pulses. if the time exceeds 40 s, dl drives high to turn the low-side mosfet on. this draws current from v out through the inductor, forcing both v out and v fb to fall. w hen v fb drops to the 500 mv threshold, the next dh on-time is triggered. after the on-time is completed the high-side mosfet is turned off and the low-side mosfet turns on, the low-side mosfet remains on until the inductor current ramps down to zero, at which point the lo w-side mosfet is turned off. because the on-times are forced to occur at intervals no greater than 40 s, the frequency will not fall below ~ 25 khz. figure 5 shows ultra-sonic power-save operation. benefits of ultrasonic power-save having a fixed minimum frequency in power-save has some significant advantages as below: ? the minimum frequency of 25 khz is outside the audible range of human ear. this makes the operation of the sic417 very quiet. ? the output voltage ripple seen in power-save mode is significant lower than conventional power-save, which improves efficiency at light loads. ? lower ripple in power-save also makes the power component selection easier. figure 6 shows the behavior under power-save and continuous conduction mode at light loads. smart power-save protection active loads may leak current from a higher voltage into the switcher output. under light load conditions with power- savepower-save enabled, this can force v out to slowly rise and reach the over-voltage threshold, resulting in a hard shutdown. smart power-save prevents this condition. w hen the fb voltage exceeds 10 % above nominal (exceeds 550 mv), the device immediately disables power-save, and dl drives high to turn on the low-side mosfet. this draws current from v out through the inductor and causes v out to fall. w hen v fb drops back to the 500 mv trip point, a normal t on switching cycle begins. this method prevents a hard ovp shutdown and also cycles energy from v out back to v in . it also minimizes operating power by avoiding forced conduction mode operation. figure 7 shows typical waveforms for the smart power-save feature. figure 4 - forced continuous mode operation figure 5 - ultrasonic power-save operation fb ripple v oltage ( v fb ) ind u ctor c u rrent dc load c u rrent fb threshold (500 m v ) dh dl on-time (t o n ) dh on-time is triggered w hen v fb reaches the fb threshold dl dri v es high w hen on-time is completed. dl remains high u ntil v fb falls to the fb threshold. fb ripple v oltage ( v fb ) ind u ctor c u rrent (0a) fb threshold (500 m v ) dh dl on-time (t o n ) dh on-time is triggered w hen v fb reaches the fb threshold after the 40 s time-o u t, dl dri v es high if v fb has not reached the fb threshold. minim u m f sw ~ 25 khz figure 6 - ultrasonic power-save operation mode
www.vishay.com 10 document number: 69062 s10-1367-rev. d, 14-jun-10 vishay siliconix sic417 current limit protection the sic417 features programmable current limit capability, which is accomplished by using the r ds(on) of the lower mosfet for current sensing. the current limit is set by r ilim resistor. the r ilim resistor connects from the i lim pin to the lx pin which is also the drain of the low-side mosfet. w hen the low-side mosfet is on, an internal ~ 10 a current flows from the i lim pin and the r ilim resistor, creating a voltage drop across the resistor. w hile the low-side mosfet is on, the inductor current flows through it and creates a voltage across the r ds(on) . the voltage across the mosfet is negative with respect to ground. if this mosfet voltage dr op exceeds the voltage across r ilim , the voltage at the i lim pin will be negative and current limit will activate. the current limit then keeps the low-side mosfet on and will not allow another high-side on-time, until the current in the low-side mosfet reduces enough to bring the i lim voltage back up to zero. this method regulates the inductor valley current at the level shown by i lim in figure 8. setting the valley current limit to 10 a results in a 10 a peak inductor current plus peak ripple current. in this situation, the average (load) current through the inductor is 10 a plus one-half the peak-to-peak ripple current. the internal 10 a current source is temperature compensated at 4100 ppm in or der to provide tracking with the r ds(on) . the r ilim value is calculated by the following equation. r ilim = 735 x i lim note that because the low-side mosfet with low r ds(on) is used for current sensing, the pcb layout, solder connections, and pcb connection to the lx node must be done carefully to obtain good results. refer to the layout guidelines for information. soft-start of pwm regulator soft-start is achieved in the p w m regulator by using an internal voltage ramp as the reference for the fb comparator. the voltage ramp is generated using an internal charge pump which drives the reference from zero to 500 mv in ~ 1.2 mv increments, using an internal ~ 500 khz oscillator. w hen the ramp voltage reaches 500 mv, the ramp is ignored and the fb comparat or switches over to a fixed 500 mv threshold. during soft -start the output voltage tracks the internal ramp, which limits the start-up inrush current and provides a controlled softstart profile for a wide range of applications. typical softstart ramp time is 850 s. during soft-start the regulat or turns off the low-side mosfet on any cycle if the inductor current falls to zero. this prevents negative inductor current, allowing the device to start into a pre-biased output. power good output the power good (p good ) output is an open-drain output which requires a pull-up resistor. w hen the output voltage is 10 % below the nominal voltage, p good is pulled low. it is held low until the output voltage returns above - 8 % of nominal. p good is held low during start-up and will not be allowed to transition high until soft-start is completed (when v fb reaches 500 mv) and typically 2 ms has passed. p good will transition low if the v fb pin exceeds + 20 % of nominal, which is also the over-voltage shutdown threshold (600 mv). p good also pulls low if the en/psv pin is low when v5v is present. output over-voltage protection over-voltage protection becomes active as soon as the device is enabled. the threshold is set at 500 mv + 20 % (600 mv). w hen v fb exceeds the ovp threshold, dl latches high and the low-side mosfet is turned on. dl remains high and the controller remains off , until the en/psv input is toggled or v5v is cycled. there is a 5 s delay built into the ovp detector to prevent false transitions. p good is also low after an ovp event. output under-voltage protection w hen v fb falls 25 % below its nominal voltage (falls to 375 mv) for eight consecutive clock cycles, the switcher is shut off and the dh and dl drives are pulled low to tristate the mosfets. the controll er stays off until en/psv is toggled or v5v is cycled. v5v uvlo, and por under-voltage lock-out (uvlo) circuitry inhibits switching and tri-states the dh/dl driver s until v5v rises above 3.9 v. an internal power-on rese t (por) occurs when v5v exceeds 3.9 v, which resets the fault latch and soft-start figure 7 - smart power-save figure 8 - valley current limit v out drifts u p to d u e to leakage c u rrent flo w ing into c out smart po w er sa v e threshold (550 m v ) fb threshold dh and dl off high-side dri v e (dh) lo w -side dri v e (dl) n ormal v out ripple v out discharges v ia ind u ctor and lo w -side mosfet single dh on-time p u lse after dl t u rn-off n ormal dl p u lse after dh on-time p u lse dl t u rns on w hen smart psa v e threshold is reached dl t u rns off fb threshold is reached i peak i load i lim time ind u ctor c u rrent
vishay siliconix sic417 document number: 69062 s10-1367-rev. d, 14-jun-10 www.vishay.com 11 counter to prepare for soft-start. the sic417 then begins a soft-start cycle. the p w m will shut off if v5v falls below 3.6 v. ldo regulator the sic417 features an int egrated ldo regulator with a programmable output voltage from 0.75 v to 5.25 v using external resistors, when an external supply is used to power v5v. the feedback pin (fbl) for the ldo is regulated to 750 mv. there is also an enable pin (enl) for the ldo that provides independent control. the ldo voltage can also be used to provide the bias volt age for the switching regulator, when v ldo is tied to v5v. more detail can be found in the on chip ldo bias section coming up. the ldo output voltage is set by the following equation. a minimum capacitance of 1 f referenced to agnd is normally required at the output of the ldo for stability. if the ldo is providing bias power to the device, then a minimum 0.1 f capacitor referenced to a gnd is required along with a minimum 1.0 f capacitor referenced to p gnd to filter the gate drive pulses. refer to the layout guideline section. ldo start-up before start-up, the ldo che cks the status of the following signals to ensure proper operation can be maintained. 1. enl pin 2. v ldo output 3. v in input voltage w hen the enl pin is high and v in is above the uvlo point, the ldo will begin start-up. during the initial phase, when the ldo output voltage is near zero, the ldo initiates a current-limited start-up (typically 85 ma) to charge the output capacitor. w hen v ldo has reached 90 % of the final value (as sensed at the fbl pin), the ldo current limit is increased to ~ 200 ma and the ldo output is quickly driven to the nominal value by the internal ldo regulator. ldo switchover function the sic417 includes a switch-ove r function for the ldo. the switch-over function is design ed to increase efficiency by using the more efficient dc-to- dc converter to power the ldo output, avoiding the less efficient ldo regulator when possible. the switch-over function connects the v ldo pin directly to the v out pin using an internal switch. w hen the switch-over is complete the ldo is turned off, which results in a power savings and maximi zes efficiency. if the ldo output is used to bias the sic417, then after switch-over the device is self-powered from the switching regulator with the ldo turned off. the switch-over logic waits for 32 switching cycles before it starts the switch-over. there are two methods that determine the switch-over of v ldo to v out . in the first method, the ldo is already in regulation and the dc-to-dc converter is later enabled. as soon as the p good output goes high, the 32 cycles are started. the voltages at the v ldo and v out pins are then compared; if the two voltages are within 300 mv of each other, the v ldo pin connects to the v out pin using an internal switch, and the ldo is turned off. in the second method, the dc-to-dc converter is already running and the ldo is enabled. in this case the 32 cycles are started as soon as the ldo reaches 90 % of its final value. at this time, the v ldo and v out pins are compared, and if within 300 mv the switch-over occurs and the ldo is turned off. benefits of having a switchover circuit the switchover function is designed to get maximum efficiency out of the dc-to-dc converter. the efficiency for an ldo is very low especially for high input voltages. using the switchover function we tie any rails connected to v ldo through a switch directly to v out . once switchover is complete ldo is turned off which saves power. this gives us the maximum efficiency out of the sic417. if the ldo output is used to bias the sic417, then after switchover the v out self biases the sic417 and operates in self-powered mode. steps to follow when using the on chip ldo to bias the sic417: ? always tie the v5v to v ldo before enabling the ldo ? enable the ldo before enabling the switcher ? ldo has a current limit of 85 ma at start-up with 12 v in , so do not connect any load between v ldo and ground ? the current limit for the ldo goes up to 200 ma once the v ldo reaches 90 % of its final values and can easily supply the required bias current to the ic. switch-over limitations on v out and v ldo because the internal switch -over circuit always compares the v out and v ldo pins at start-up, there are limitations on permissible combinations of v out and v ldo . consider the case where v out is programmed to 1.5 v and v ldo is programmed to 1.8 v. after start-up, the device would connect v out to v ldo and disable the ldo, since the two voltages are within the 300 mv switch-over window. figure 9 - ldo start-up figure 10 - ldo start-up v ldo r ldo1 r ldo2 to fbl pin v ldo = 750 m v x 1+ r ldo1 r ldo2 ( ) constant c u rrent start u p v v ldo final 90 % of v v ldo final v oltage reg u lating w ith ~ 200 ma c u rrent limit
www.vishay.com 12 document number: 69062 s10-1367-rev. d, 14-jun-10 vishay siliconix sic417 to avoid unwanted switch-over, the minimum difference between the voltages for v out and v ldo should be 500 mv. it is not recommended to use the switch-over feature for an output voltage less than 3 v since this does not provide sufficient voltage for the gate-source drive to the internal p-channel switch-over mosfet. switch-over mosfet parasitic diodes the switch-over mosfet contai ns parasitic diodes that are inherent to its construction, as shown in figure 11. there are some important design rules that must be followed to prevent forward bias of these diodes. the following two conditions need to be satisfied in order for the parasitic diodes to stay off. ? v5v v ldo ? v5v v out if either v ldo or v out is higher than v5v, then the respective diode will turn on and the sic417 operating current will flow through this diode. this has the potential of damaging the device. enl pin and v in uvlo the enl pin also acts as the switcher under-voltage lockout for the v in supply. the v in uvlo voltage is programmable via a resistor divider at the v in , enl and a gnd pins. enl is the enable/disable signal for the ldo. in order to implement the v in uvlo there is also a timing requirement that needs to be satisfied. if the enl pin transitions low within 2 switching cycles and is < 1 v, then the ldo will turn of f but the switcher remains on. if enl goes below the v in uvlo threshold and stays above 1 v, then the switcher will turn off but the ldo remains on. the v in uvlo function has a typical threshold of 2.6 v on the v in rising edge. the falling edge threshold is 2.4 v. note that it is possible to op erate the switcher with the ldo disabled, but the enl pin must be below the logic low threshold (0.4 v maximum). enl logic control of pwm operation w hen the enl input is driven above 2.6 v, it is impossible to determine if the ldo output is going to be used to power the device or not. in self-powered operation where the ldo will power the device, it is nece ssary during the ldo start-up to hold the p w m switching off until the ldo has reached 90 % of the final value. this is to prevent overloading the current-limited ldo output during the ldo start-up. however, if the switcher was previously operating (with en/ psv high but enl at ground, a nd v5v supplied externally), then it is undesirable to shut down the switcher. to prevent this, when the enl input is taken above 2.6 v (above the v in uvlo threshold), the internal logic checks the p good signal. if p good is high, then the switcher is already running and the ldo will run through the start-up cycle without affecting the switcher. if p good is low, then the ldo will not allow any p w m switching until the ldo output has reached 90 % of it's final value. on-chip ldo bias the sic417 the following steps must be followed when using the onchip ldo to bias the device. ? connect v5v to v ldo before enabling the ldo. ? the ldo has an initial current limit of 85 ma at start-up with 12 v in , therefore, do not connect any external load to v ldo during start-up. ? w hen v ldo reaches 90 % of its final value, the ldo current limit increases to 200 ma. at this time the ldo may be used to supply the required bias current to the device. ? switching will be held off until v ldo reaches regulation. attempting to operate in self-powered mode in any other configuration can cause unpr edictable results and may damage the device. design procedure w hen designing a switch mode power supply, the input voltage range, load current, switching frequency, and inductor ripple current must be specified. the maximum input voltage (v inmax ) is the highest specified input voltage. the minimum input voltage (v inmin ) is determined by the lowest input voltage after evaluating the voltage drops due to connectors, fuses, switches, and pcb traces. the following parameters define the design: ? nominal output voltage (v out ) ? static or dc output tolerance ? transient response ? maximum load current (i out ) there are two values of load current to evaluate - continuous load current and peak load current. continuous load current relates to thermal stresses whic h drive the selection of the inductor and input capacitors. peak load current determines instantaneous component stresses and filtering requirements such as inductor saturation, output capacitors, and design of the current limit circuit. the following values are used in this design: ? v in = 12 v 10 % ? v out = 1.05 v 4 % ? f s w = 250 khz ? load = 10 a maximum figure 11 - switch-over mosfet parasitic diodes v out v ldo v 5 v parastic diode parastic diode s w itcho v er mosfet s w itcho v er control
vishay siliconix sic417 document number: 69062 s10-1367-rev. d, 14-jun-10 www.vishay.com 13 frequency selection selection of the switching frequency requires making a trade-off between the size and cost of the external filter components (inductor and output capacitor) and the power conversion efficiency. the desired switching frequency is 250 khz which results from using component selected for optimum size and cost. a resistor (r ton ) is used to program the on-time (indirectly setting the frequency) using the following equation. to select r ton , use the maximum value for v in , and for t on use the value associated with maximum v in . t on = 318 ns at 13.2 v in , 1.05 v out , 250 khz substituting for r ton results in the following solution r ton = 154.9 k , use r ton = 154 k . inductor selection in order to determine the indu ctance, the ripple current must first be defined. low inductor values result in smaller size but create higher ripple current which can reduce efficiency. higher inductor values will reduce the ripple current and voltage and for a given dc resistance are more efficient. however, larger inductance translates directly into larger packages and higher cost. cost, size, output ripple, and efficiency are all used in the selection process. the ripple current will also set the boundary for power-save operation. the switching w ill typically enter power-save mode when the load current decreases to 1/2 of the ripple current. for example, if ripple current is 4 a then power-save operation will typically start for loads less than 2 a. if ripple current is set at 40 % of maximum load current, then power- save will start for loads less than 20 % of maximum current. the inductor value is typically selected to provide a ripple current that is between 25 % to 50 % of the maximum load current. this provides an optimal trade-off between cost, efficiency, and transient performance. during the dh on-time, voltage across the inductor is (v in -v out ). the equation for determining inductance is shown next. example in this example, the inductor ripple current is set equal to 50 % of the maximum load current. thus ripple current will be 50 % x 10 a or 5 a. to find the minimum inductance needed, use the v in and t on values that correspond to v inmax. a slightly larger value of 0.88 h is selected. this will decrease the maximum i ripple to 4.4 a. note that the inductor must be rated for the maximum dc load current plus 1/2 of the ripple current. the ripple current under minimum v in conditions is also checked using the following equations. capacitor selection the output capacitors are chosen based on required esr and capacitance. the maximum esr requirement is controlled by the output ripple requirement and the dc tolerance. the output voltage has a dc value that is equal to the valley of the output rippl e plus 1/2 of the peak-to-peak ripple. change in the output ripple voltage will lead to a change in dc voltage at the output. the design goal is that the output voltage regulation be 4 % under static conditions. the internal 500 mv reference tolerance is 1 %. allowing 1 % tolerance from the fb resistor divider, this allows 2 % tolerance due to v out ripple. since this 2 % error comes from 1/2 of the ripple voltage, the allowable ripple is 4 %, or 42 mv for a 1.05 v output. the maximum ripple current of 4.4 a creates a ripple voltage across the esr. the maximum esr value allowed is shown by the following equations. the output capacitance is usual ly chosen to meet transient requirements. a worst-case load release, from maximum load to no load at the exact moment when inductor current is at the peak, determines the required capacitance. if the load release is instantaneous (load changes from maximum to zero in < 1 s), the output capacitor must absorb all the inductor's stored energy. this will cause a peak voltage on the capacitor according to the following equation. assuming a peak voltage v peak of 1.150 (100 mv rise upon load release), and a 10 a load release, the required capacitance is shown by the next equation. if the load release is relatively slow, the output capacitance can be reduced. at heavy loads during normal switching, when the fb pin is above th e 500 mv reference, the dl r ton = (t o n - 10 ns) x v i n 25 pf x v out t o n = v out v i n max. x f sw l = ( v i n - v out ) x t o n i ripple l = (13.2 - 1.05) x 31 8 ns 5 a = 77 h t o n _ v i n mi n = 25 pf x r to n x v out v i n mi n i ripple = ( v i n - v out ) x t o n l i ripple_ v i n = (10. 8 - 1.05) x 3 8 4 ns 0. 88 h = 4.25 a esr max = v ripple i ripplemax esr max = 9.5 m = 42 m v 4.4 a cout mi n = l (i out + x i ripplemax ) 2 ( v peak ) 2 - ( v out ) 2 1 2 cout mi n = 0. 88 h (10 + x 4.4) 2 (1.15) 2 - (1.05) 2 cout mi n = 595 f 1 2
www.vishay.com 14 document number: 69062 s10-1367-rev. d, 14-jun-10 vishay siliconix sic417 output is high and the low-si de mosfet is on. during this time, the voltage across the inductor is approximately - v out . this causes a down-slope or falling di/dt in the inductor. if the load di/dt is not much faster than the - di/dt in the inductor, then the inductor current will tend to track the falling load current. this will reduce the excess inductive energy that must be absorbed by the output capacitor, therefore a smaller capacitance can be used. the following can be used to calculate the needed capacitance for a given di load /dt: peak inductor current is shown by the next equation. i lpk = i max + 1/2 x i ripplemax i lpk = 10 + 1/2 x 4.4 = 12.2 a rate of change of load current = di load /dt i max = maximum load release = 10 a example this would cause the output current to move from 10 a to zero in 4 s as shown by the following equation. note that c out is much smaller in this example, 379 f compared to 595 f based on a worst-case load release. to meet the two design criteria of minimum 379 f and maximum 9 m esr, select two capacitors rated at 220 f and 15 m esr. it is recommended that an additional small capacitor be placed in parallel with c out in order to filter high frequency switching noise. stability considerations unstable operation is possible with adaptive on-time controllers, and usually takes the form of double-pulsing or esr loop instability. double-pulsing occurs due to switching noise seen at the fb input or because the fb ripple voltage is too low. this causes the fb comparator to trigger prematurely after the 250 ns minimum off-time has expired. in extreme cases the noise can cause three or more successive on-times. double-pulsing will result in higher ripple voltage at the output, but in most applications it will not affect operation. this form of instability can usually be avoided by providing the fb pin with a smooth, clean ripple signal that is at least 10 mv p-p , which may dictate the need to increase the esr of the output capacitors. it is also imperative to provide a proper pcb layout as discussed in the layout guidelines section. another way to eliminate doubling-pulsing is to add a small (~ 10 pf) capacitor across the upper feedback resistor, as shown in figure 13. this capacitor should be left unpopulated until it can be confirmed that double-pulsing exists. adding the c top capacitor will couple more ripple into fb to help eliminate the problem. an opt ional connection on the pcb should be available for this capacitor. esr loop instability is caused by insufficient esr. the details of this stability issue are discussed in the esr requirements section. the best method for checking stability is to apply a zero-to-full load transient and observe the output voltage ripple envelope for overshoot and ringing. ringing for more than one cycle after the initial step is an indication that the esr should be increased. one simple way to solve this problem is to add trace resistance in the high current output path. a side effect of adding trace resistance is output decreased load regulation. esr requirements a minimum esr is required for two reasons. one reason is to generate enough output ripple voltage to provide10 mv p-p at the fb pin (after the resistor divider) to avoid double- pulsing. the second reason is to prevent instability due to insufficient esr. the on-time control regulates the valley of the output ripple voltage. this ripple voltage is the sum of the two voltages. one is the ripple g enerated by the esr, the other is the ripple due to capacitive charging and discharging during the switching cycle. for most applications the minimum esr ripple voltage is dominated by the output capacitors, typically sp or po scap devices. for stability the esr zero of the output capacitor should be lower than approximately one-third the switching frequency. the formula for minimum esr is shown by the following equation. for applications using ceramic output capacitors, the esr is normally too small to meet the above esr criteria. in these applications it is necessary to add a small virtual esr network composed of two capacitors and one resistor, as shown in figure 14. this network creates a ramp voltage c out = i lpk x l x - x dt 2 ( v pk - v out ) i lpk v out i max dl load load dl load dt = 2.5 a s c out = 12.2 x 0. 88 h x - x 1 s 2 (1.15 - 1.05) 12.2 1.05 10 2.5 c out = 379 f figure 13 - capacitor coupling to fb pin v out r 1 r 2 to fb pin c top esr mi n = 3 2 x x c out x f sw
vishay siliconix sic417 document number: 69062 s10-1367-rev. d, 14-jun-10 www.vishay.com 15 across c l , analogous to the ramp voltage generated across the esr of a standard capaci tor. this ramp is then capacitive-coupled into the fb pin via capacitor c c . dropout performance the output voltage adjusts r ange for continuous-conduction operation is limited by the fixed 250 ns (typical) minimum off-time of the one-shot. w hen working with low input voltages, the duty-factor limit must be calculated using worst-case values for on and off times. the duty-factor limitation is shown by the next equation. the inductor resistance and mo sfet on-state voltage drops must be included when performing worst-case dropout duty-factor calculations. system dc accuracy (v out controller) three factors affect v out accuracy: the trip point of the fb error comparator, the ripple voltage variation with line and load, and the external resistor tolerance. the error comparator off set is trimmed so that under static conditions it trips when the feedback pin is 500 mv, 1 %. the on-time pulse from the sic417 in the design example is calculated to give a pseudo-fixed frequency of 250 khz. some frequency variation with line and load is expected. this variation changes the output ripple voltage. because constant on-time converters regulate to the valley of the output ripple, ? of the output ripple appears as a dc regulation error. for example, if the output ripple is 50 mv with v in = 6 v, then the measured dc output will be 25 mv above the comparator trip point. if the ripple increases to 80 mv with v in = 25 v, then the measured dc output will be 40 mv above the comparator trip. the best way to minimize this effect is to minimize the output ripple. to compensate for valley regulation, it may be desirable to use passive droop. take the feedback directly from the output side of the inductor an d place a small amount of trace resistance between the inductor and output capacitor. this trace resistance should be optimized so that at full load the output droops to near the lower regulation limit. passive droop minimizes the required output capacitance because the voltage excursions due to load steps are reduced as seen at the load. the use of 1 % feedback resistors contributes up to 1 % error. if tighter dc accuracy is required, 0.1 % resistors should be used. the output inductor value may change with current. this will change the output ripple and therefore will have a minor effect on the dc output voltage. the output esr also affects the output ripple and thus has a minor effect on the dc output voltage. switching frequency variations the switching frequency will vary depending on line and load conditions. the line variations are a result of fixed propagation delays in the on-time one-shot, as well as unavoidable delays in the external mosfet switching. as v in increases, these factors make the actual dh on-time slightly longer than the ideal on-time. the net effect is that frequency tends to falls slightly with increasing input voltage. the switching frequency also varies with load current as a result of the power losses in the mosfets and the inductor. for a conventional p w m constant-frequency converter, as load increases the duty cycle also increases slightly to compensate for ir and swit ching losses in the mosfets and inductor. a constant on-time converter must also compensate for the same losses by increasing th e effective duty cycle (more time is spent drawing energy from v in as losses increase). the on-time is essentiall y constant for a given v out /v in combination, to off set the losses the off-time will tend to reduce slightly as load incr eases. the net effect is that switching frequency increases slightly with increasing load. figure 14 - virtual esr ramp current c out high- side lo w - side fb pin l r1 r2 r l c l c c duty = t o n (mi n ) t o n (mi n ) x t off(max)
www.vishay.com 16 document number: 69062 s10-1367-rev. d, 14-jun-10 vishay siliconix sic417 sic417 evaluation board schematic figure 15. evaluation board schematic v o v i n v 5 v v 5 v v 5 v c26 4.7 f r15 10k c9 10 f m4 1 1 q1 si4 8 12bdy j3 pro b e test pin 1 2 5 3 4 p12 ldtrg 1 b3 v o 1 j6 pro b e test pin j6 pro b e test pin 1 2 5 3 4 r13 1k + c12 150 f + r5 100k r39 0r c5 0.1 f + c1 8 220 f + p7 p7 p good 1 r11 0 c11 0.1 f + c23 220 f + c29 22 f c14 0.1 f c24 10n * b1 v i n 1 r4 1r01 b2 v i n _g n d 1 u1 sic417 u1 sic417 fb 1 fbl 2 v 5 v 3 ag n d 4 v out 5 v i n 6 v ldo 7 bst 8 v i n 9 v i n 10 v i n 11 dh 12 lx 13 dl 14 pg n d 15 pg n d 16 lx 24 lx 23 pg n d 22 pg n d 21 pg n d 20 pg n d 19 pg n d 1 8 pg n d 17 e n l 32 to n 31 ag n d 30 e n /ps v 29 lx 2 8 ilim 27 pgd 26 lx 25 lx 33 v i n 34 ag n d 35 p11 v o_g n d 1 + c17 220 f + c7 0.1 f c7 r3 1k p10 v o 1 m3 1 1 p1 v i n 1 c19 1 * r9 * p9 v ctrl 1 c30 47 pf p3 v 5 v p3 v 5 v 1 j2 pro b e test pin 1 2 5 3 4 r6 100k r7 0 c20 10 f r 8 10k p 8 step_i_sense 1 p2 v i n _g n d 1 r40 1 j7 pro b e test pin 1 2 5 3 4 c31 100 pf * + c16 220 f + r1 300k * c13 0.01 f m2 1 1 c27 4.7 f * c10 10 f p5 e n _ps v p5 1 c6 0.1 f c1 22 f m1 1 1 r29 10k c 8 10 f c15 10 f c25 6 8 pf r10 10k r10 10k p6 e n l 1 c22 10 f j5 pro b e test pin 1 2 5 3 4 l1 1 h r2 300k * j4 pro b e test pin 1 2 5 3 4 c3 22 f r23 7.15k r23 7.15k r30 75k j1 pro b e test pin j1 pro b e test pin 1 2 5 3 4 c21 10 f c32 1n c4 22 f b4 b4 v o_g n d 1 p4 v ldo 1 c2 22 f c2 8 0.1 f r12 57.6k
vishay siliconix sic417 document number: 69062 s10-1367-rev. d, 14-jun-10 www.vishay.com 17 bill of materials reference designator value voltage footprint part number manufacturer b1, b2, b3, b4 solder-banana 575-4 keystone c29 22 f 16 v sm/c_1210 grm32er71c226me18l murata c5 0.1 f 10 v sm/c_0402 c0402c104k8rac7867 vishay c6 0.1 f 10 v sm/c_0805 c0402c104k8rac7867 vishay c11, c14, c28 0.1 f 50 v sm/c_0603 vj0603y104kxac w 1bc vishay c8, c9, c10 10 f 25 v sm/c_1210 tmk325b7106mn-t taiyo yuden c12 150 f 35 v d8x11.5-d0.6x3.5 eeu-fm1v151 panasonic c13 0.01 f 50 v sm/c_0402 vj0402y103kxac w 1bc vishay c15, c20, c21, c22 10 f 16 v sm/c_1206 grm31cr71c106kac7l c16, c17, c18, c23 220 f 10 v 595d-d 593d227x0010e2te3 vishay c19 1 f sm/c_0603 c24 10 nf sm/c_0603 c25 100 pf 50 v sm/c_0402 vj0402a101jxac w 1bc vishay c26 4.7 f 10 v sm/c_0805 lmk212b7475kg-t taiyo yuden c27 4.7 f 10 v sm/c_0805 lmk212b7475kg-t taiyo yuden c30 47 pf sm/c_0402 vj0402a470jxac w 1bc c31 100 pf sm/c_0402 vj0402y101kxqc w 1bc vishay c32 1000 pf 50 v sm/c_0805 vj0805a102kxa vishay j1, j2, j3, j4, j5, j6, j7 probe test pin lecroy probe pin pk007-015 lecroy l1 1 h ihlp4040 ihlp4040dzer1r0m01 vishay m1, m2, m3, m4 m hole2 stacking spacer 8834 keystone p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12 v in , gnd etc. probe hook 1540-2 keystone r1 300k 50 v sm/c_0603 crc w 060310k0fkea vishay r2 300k 50 v sm/c_0603 crc w 06030000fkea vishay r3, r13 1k sm/c_0402 crc w 04021k00fked vishay r6 100k 50 v sm/c_0603 crc w 0603100kfkea vishay r7, r11 0r sm/c_0603 crc w 06030000z0ea vishay r8, r10, r15, r29 10k sm/c_0603 mcr03ezhf1002 rohm r9 sm/c_0603 r12 57.6k sm/c_0603 crc w 060357k6fkea vishay r23 7.15k sm/c_0603 crc w 06037k15fkea vishay r30 75k sm/c_0603 crc w 0603154kfkea vishay r39 0r sm/c_0402 crc w 04020000z0ed vishay r40 1 sm/c_0805 crc w 08051r00fnea vishay u1 sic417 qfn5x5_32 leads + 3 pads vishay optional cicuitry for transient response testing q1 si4812bdy 30 v so-8 si4812bdy vishay r4 1r01 200 v c_2512 crc w 25121r00fkta vishay r5 100k 50 v sm/c_0603 crc w 0603100kfkea vishay c7 0.1 f 50 v sm/c_0603 vj0603y104kxac w 1bc vishay c1, c2, c3, c4 22 f 16 v sm/c_1210 grm32er71c226me18l murata
www.vishay.com 18 document number: 69062 s10-1367-rev. d, 14-jun-10 vishay siliconix sic417 pcb layout of the evaluation board figure 16. pcb layout - top layer figure 18. pcb layout - midlayer2 figure 17. pcb layout - midlayer1 figure 19. pcb layout - bottom layer
vishay siliconix sic417 document number: 69062 s10-1367-rev. d, 14-jun-10 www.vishay.com 19 package dimensions and marking info vishay siliconix maintains worldwide manufacturing capability. pr oducts may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?69062 . 5.000 0.075 5.000 0.075 + pin # 1 (laser marked) top v ie w a c 0.10 c 0.0 8 c 0.900 0.100 0.050 0.000 b 0.200 ref. bare copper 0.460 0.10 c a b 0.500 0.460 3.4 8 0 0.100 r f u ll 17 24 16 c l c l 9 25 32 8 1.4 8 5 0.100 0.250 0.050 1.660 0.100 bottom v ie w 1.050 0.100 0.400 0.100 r0.200 pin 1 i.d. 1.970 0.100
document number: 64714 www.vishay.com revision: 29-dec-08 1 package information vishay siliconix powerpak ? mlp55-32l case outline notes 1. use millimeters as the primary measurement. 2. dimensioning and tolerances conform to asme y14.5m. - 1994. 3. n is the number of terminals. nd is the number of terminals in x-direction and ne is the number of terminals in y-direction. 4. dimension b applies to plated terminal and is m easured between 0.20 mm and 0.25 mm from terminal tip. 5. the pin #1 identifier must be existed on the top surface of the package by using i ndentation mark or other feature of package body. 6. exact shape and size of this feature is optional. 7. package warpage max. 0.08 mm. 8. applied only for terminals. b y marking e pin 1 dot top v ie w d (5 mm x 5 mm) 32l t/slp e2 - 2 ( n d-1) xe ref. bottom v ie w side v ie w d2 - 1 r0.200 pin #1 identification b e d2 - 4 d2 - 3 e2 - 3 d4 9 24 25 32 a 0.10 c b 2x 0.0 8 c c a a2 a1 b ( n d-1) xe ref. l 0.36 0.360 5 6 0.10 c a b 4 d2 - 2 e2 - 1 0.10 c a 2x 8 17 16 0.45 1 millimeters inches dim min. nom. max. min. nom. max. a 0.80 0.85 0.90 0.031 0.033 0.035 a1 (8) 0.00 - 0.05 0.000 - 0.002 a2 0.20 ref. 0.008 ref. b (4) 0.20 0.25 0.30 0.078 0.098 0.011 d 5.00 bsc 0.196 bsc e 0.50 bsc 0.019 bsc e 5.00 bsc 0.196 bsc l 0.35 0.40 0.45 0.013 0.015 0.017 n (3) 32 32 nd (3) 88 ne (3) 88 d2 - 1 3.43 3.48 3.53 0.135 0.137 0.139 d2 - 2 1.00 1.05 1.10 0.039 0.041 0.043 d2 - 3 1.00 1.05 1.10 0.039 0.041 0.043 d2 - 4 1.92 1.97 2.02 0.075 0.077 0.079 e2 - 1 3.43 3.48 3.53 0.135 0.137 0.139 e2 - 2 1.61 1.66 1.71 0.063 0.065 0.067 e2 - 3 1.43 1.48 1.53 0.056 0.058 0.060 ecn: t-08957-rev. a, 29-dec-08 dwg: 5983
document number: 91 000 www.vishay.com revision: 11-mar-11 1 disclaimer legal disclaimer notice vishay all product, product specifications and data ar e subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicab le law, vishay disc laims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, incl uding without limitation specia l, consequential or incidental dama ges, and (iii) any and all impl ied warranties, including warran ties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of pro ducts for certain types of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in gene ric applications. such statements are not binding statements about the suitability of products for a partic ular application. it is the customers responsibility to validate that a particu lar product with the properties described in th e product specification is su itable for use in a particul ar application. parameters provided in datasheets an d/or specifications may vary in different applications and perfo rmance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product co uld result in person al injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding the design or manufact ure of the part. please contact authorized vishay personnel t o obtain written terms and conditions regarding products designed fo r such applications. no license, express or implied, by estoppel or otherwise, to any intelle ctual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

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